About Me

Welcome to my personal website! Here, I present my proficiency in Electrical Engineering, emphasizing my expertise in Physical Design, Static Timing Analysis, and SoC Design. As a passionate VLSI enthusiast, I am excited and consider myself privileged to be an ongoing graduate student at Texas A&M University, pursuing a Master's degree in Electrical Engineering with a specialization in VLSI Design. I pursued my Bachelor's degree in Electronics and Communication Engineering from M.S. Ramaiah University of Applied Sciences. I worked as an Electrical Engineer Intern at Raman Research Institute, where I was responsible for power supply testing and timing analysis.
I find inspiration in taking on challenges and have a strong enthusiasm for acquiring new skills and techniques. I am looking forward to connecting with professionals in this field to learn more about the industry and potential career paths.
For more information, please feel free to refer to my resume. Furthermore, I keep an updated GitHub website where I showcase my projects.
Thank you for visiting my website! If you have any questions or would like to know more about my work or projects, please feel free to reach out.

Experience

Education

Skills

  • November 2021 - July 2022
    RAMAN RESEARCH INSTITUTE-Electrical Engineer Intern
    • I was involved in the Design of Power supply for Charge Sensitive Pre-Amplifier and Amp-tek-PH300 chip.
    • Conducted testing of the Amp-tek PH300 chip to determine its upper threshold voltage and lower threshold voltage. Implemented timing checks and ADC calibration on digital cards.
    • Through these experiences, I gained valuable insights into the intricacies of hardware testing.
    • May 2020 - June 2020
      Agimus Technologies-Virtual Intern
      • Developed Machine Learning algorithms utilizing Tensor Flow to classify various data. Specifically, I focused on image classification using webcam images and human activity learning using mobile phone data for real-time data analysis.
      • These projects demonstrate my expertise in Machine Learning and showcase my ability to apply advanced algorithms to real-world applications.
    • June 2019 - August 2019
      RAMAN RESEARCH INSTITUTE-Electrical Engineer Intern
      • Designed and developed a receiver chain incorporating Low-Noise Amplifiers, Optical fibers, and filters, operating within a bandwidth of 1350-1650 MHz.
      • The analog receiver was connected to a horn antenna for input and utilized high-speed optical fibers to interface with a Software Defined Radio (SDR) for digitization and data recording.
  • Master's Degree
    August 2022 - Current
    Texas A&M University, College Station, Texas
    Pursuing my Masters in Electrical Engineering
    Specialisation in VLSI Design (Running GPA 3.5)
  • Bachelor's Degree
    August 2017 - August 2021
    M.S. Ramaiah University of Applied Sciences, Bangalore, India
    Pursued Electronics and Communication Engineering
    Graduated with a CGPA 9.11
  • Senior Secondary Education
    August 2015 - August 2017
    Narayana PU College, Bangalore, India
    89%
  • Secondary Education
    August 2015
    Sri Chaitanya Techno School, Bangalore, India
    CGPA 9.6
  • Design Tools
    Schematic & Layout (Cadence Virtuoso)
    Digital Design (Vivado Design Suite)
  • EDA Tools
    Synthesis (Synopsys Design Compiler, YOSYS Synthesis Tool)
    Place and Route (Cadence Innovus, QRouter 1.4)
  • Static Timing Analysis Tools
    STA (Synopsys Primetime, OpenSTA, Vesta)
  • Simulation Tools
    MATLAB, Simulink
  • Languages
    Python, TCL, PERL, Verilog

My Projects

Design and Synthesis of a Cruise Control Logic

Designed a Finite State Machine model based Cruise Control Logic and synthesized it in 180nm technology.SDC constraints were set (Input Drive Strength, Output Capacitance Load, Clock period and Input delay) resulting in an overall cell area of 10.463mm². Achieved a maximum slack path of 3.8ns and a minimum slack path of 0.13ns.

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Characterization of D Flip-flop

Created testbench and executed post layout simulation to analyse delay characteristics and setup time of a D Flip-Flop. Strategically optimized logical effort and transistor sizing, resulting in a rise delay of 0.649ns, a fall delay of 0.652ns, and achieving a rise/fall delay difference of 0.32%, (well below the design specification of 10%) and setup time of 0.28ns.

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Place and Route of 2:1 Analog Multiplexer

Created an RTL code for the 2:1 Analog Multiplexer and built its custom layout using the Sky130 library.Modified the LEF file and layout dimensions, implemented a Floorplan, Detailed Placement, Power Distributed Network design, Routing, and DRC verification, resulting in a final layout of the Analog Multiplexer, achieving a macro height of 5.444 µm.

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Cell Characterisation using spectre

Characterization of standard cells used in the design of the pipelined adders. Characterized the typical cell's propagation delay and input capacitance by doing circuit simulations at the transistor level.

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Design of Virtual Piano using PiezoElectric Sensors

The aim of this project was to create a musical instrument using piezoelectric sensors connected to an Arduino board.

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Development of Passive Radar System

Created an analog receiver chain using low-noise amplifier and a bandpass filter with a 2 MHz bandwidth. The digital part of the setup involved a Software Defined Radio (SDR) equipped with an 8-bit ADC for digitization. The output from the SDR was channeled to an Nvidia Jetson Nano Graphics Processing Unit (GPU) to enable real-time data processing by means of an Auto-Correlation Spectrometer. To optimize this system, I implemented multi-threaded parallel programming in Python, utilizing TensorFlow for the calculation of the signal's target velocity and acceleration.

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Compressive Sensing of 1-D signals and 2-D images

A compressed sensing method based on L-1 optimization for 1-D signals and 2-D images was created with multiple transforms used to identify the optimum recovery technique.

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My Certifications

UDEMY- VSD Static Timing Analysis - I

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UDEMY- VSD-Physical Design Webinar using EDA tool 'Proton'

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UDEMY- VSD-Physical Design Flow

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Cadence- Basic Static Timing Analysis v2.0

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UDEMY- Mixed Signal Physical Design Flow with sky130

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Contact Me

EMAIL ME AT

shirisha_2022@tamu.edu


LinkedIn

Github

Download Resume